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第一次提交：完成了网关的单路485数据采集，还有以太网链接和MQTT配置，实现数据上报和命令下发，差一个断网储存

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Wang Beihong
2026-02-01 18:31:06 +08:00
commit b284cb4953
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7
components/ETH_CH390H/CMakeLists.txt Normal file
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idf_component_register(SRCS
"ETH_CH390H.c"
"esp_eth_mac_ch390.c"
"esp_eth_phy_ch390.c"
INCLUDE_DIRS "include"
REQUIRES esp_eth esp_netif driver esp_timer STATUS_LED
)

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components/ETH_CH390H/ETH_CH390H.c Normal file
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/*
* 文件: ETH_CH390H.c
* 描述: CH390H SPI 以太网模块初始化与事件处理封装。
*
* 功能:
* - 初始化 SPI 总线并配置 CH390H 设备
* - 安装并启动 esp-eth 驱动
* - 注册以太网事件回调（连接/断开/启动/停止）和获取 IP 回调
*
* 用法:
* 1. 在 app_main() 中调用 eth_init() 完成初始化，例如：
* eth_init();
* 2. 如需自定义 GPIO/SPI 配置，可修改本文件顶部的宏定义。
* 3. 如需自定义事件处理，修改 eth_event_handler 或 got_ip_event_handler。
*
* 注意:
* - 本模块使用 esp_netif 和 esp_event，调用前请确保没有重复初始化。
* - 调试时可通过调整 mac_config.rx_task_stack_size 或 SPI_CLOCK_MHZ 优化性能。
*/
#include "ETH_CH390H.h"
#include "STATUS_LED.h"
static const char *TAG = "eth_ch390h";
/* 事件处理函数
* 处理 esp-eth 发出的以太网状态事件：
* - ETHERNET_EVENT_CONNECTED : 已连接（物理链路/链路层可用）
* - ETHERNET_EVENT_DISCONNECTED : 断开（物理链路丢失）
* - ETHERNET_EVENT_START : 以太网驱动启动
* - ETHERNET_EVENT_STOP : 以太网驱动停止
* 参数：
* arg - 注册时传入的参数（当前未使用）
* event_base - 事件基（ETH_EVENT）
* event_id - 事件 id
* event_data - 事件相关数据（视事件而定）
*/
static void eth_event_handler(void *arg, esp_event_base_t event_base,
int32_t event_id, void *event_data)
{
switch (event_id)
{
case ETHERNET_EVENT_CONNECTED:
ESP_LOGI(TAG, "以太网连接成功");
status_led_set(1, 1); // LED1 常亮：物理连接正常
break;
case ETHERNET_EVENT_DISCONNECTED:
ESP_LOGI(TAG, "以太网断开连接");
status_led_blink_mode(1, 1); // LED1 快闪：网络断开
break;
case ETHERNET_EVENT_START:
ESP_LOGI(TAG, "以太网开始工作");
break;
case ETHERNET_EVENT_STOP:
ESP_LOGI(TAG, "以太网停止工作");
break;
default:
break;
}
}
/* 获取 IP 回调
* 当网口获取到 IP（DHCP 或静态）时调用，打印分配到的 IP 信息。
* 参数同上，event_data 可转换为 ip_event_got_ip_t* 来读取 ip 信息。
*/
static void got_ip_event_handler(void *arg, esp_event_base_t event_base,
int32_t event_id, void *event_data)
{
ip_event_got_ip_t *event = (ip_event_got_ip_t *)event_data;
ESP_LOGI(TAG, "获取到的IP: " IPSTR, IP2STR(&event->ip_info.ip));
status_led_set(1, 1); // LED1 常亮：IP获取成功，网络就绪
}
/* eth_init
* 初始化并启动 CH390H 以太网设备的封装函数：
* 1. 初始化网络接口与默认事件循环
* 2. 配置并初始化 SPI 总线（供 CH390H 使用）
* 3. 配置 CH390H 的 mac/phy，并安装 esp-eth 驱动
* 4. 将 esp-netif 绑定到以太网驱动，并注册事件回调
* 5. 启动以太网驱动
*
* 注意：
* - 若需要修改引脚或 SPI 频率，可在文件顶部宏中调整
* - 可根据需要调整 mac_config、phy_config 中的参数以优化性能
*/
void eth_init(void)
{
esp_netif_init();
esp_event_loop_create_default();
esp_netif_config_t cfg = ESP_NETIF_DEFAULT_ETH();
esp_netif_t *eth_netif = esp_netif_new(&cfg);
/* 设置以太网设备在 DHCP/路由器中的主机名（需在启动前设置） */
esp_netif_set_hostname(eth_netif, "Distributed Collector Gateway");
gpio_install_isr_service(0);
spi_bus_config_t buscfg = {
.mosi_io_num = ETH_MOSI_GPIO,
.miso_io_num = ETH_MISO_GPIO,
.sclk_io_num = ETH_SCLK_GPIO,
.quadwp_io_num = -1,
.quadhd_io_num = -1,
};
ESP_ERROR_CHECK(spi_bus_initialize(SPI_HOST, &buscfg, SPI_DMA_CH_AUTO));
spi_device_interface_config_t spi_devcfg = {
.mode = 0,
.clock_speed_hz = SPI_CLOCK_MHZ * 1000 * 1000,
.spics_io_num = ETH_CS_GPIO,
.queue_size = 20,
};
eth_ch390_config_t ch390_config = ETH_CH390_DEFAULT_CONFIG(SPI_HOST, &spi_devcfg);
ch390_config.int_gpio_num = ETH_INT_GPIO;
eth_mac_config_t mac_config = ETH_MAC_DEFAULT_CONFIG();
mac_config.rx_task_stack_size = 4096;
esp_eth_mac_t *mac = esp_eth_mac_new_ch390(&ch390_config, &mac_config);
eth_phy_config_t phy_config = ETH_PHY_DEFAULT_CONFIG();
esp_eth_phy_t *phy = esp_eth_phy_new_ch390(&phy_config);
esp_eth_config_t eth_config = ETH_DEFAULT_CONFIG(mac, phy);
esp_eth_handle_t eth_handle = NULL;
ESP_ERROR_CHECK(esp_eth_driver_install(&eth_config, &eth_handle));
ESP_ERROR_CHECK(esp_netif_attach(eth_netif, esp_eth_new_netif_glue(eth_handle)));
esp_event_handler_register(ETH_EVENT, ESP_EVENT_ANY_ID, &eth_event_handler, NULL);
esp_event_handler_register(IP_EVENT, IP_EVENT_ETH_GOT_IP, &got_ip_event_handler, NULL);
ESP_ERROR_CHECK(esp_eth_start(eth_handle));
}

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components/ETH_CH390H/esp_eth_mac_ch390.c Normal file
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/*
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*
* SPDX-FileContributor: 2024-2025 Sergey Kharenko
* SPDX-FileContributor: 2024-2025 Espressif Systems (Shanghai) CO LTD
*/
#include <string.h>
#include <stdlib.h>
#include <sys/cdefs.h>
#include "driver/gpio.h"
#include "driver/spi_master.h"
#include "esp_attr.h"
#include "esp_log.h"
#include "esp_check.h"
#include "esp_eth_driver.h"
#include "esp_timer.h"
#include "esp_system.h"
#include "esp_intr_alloc.h"
#include "esp_heap_caps.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
#include "ch390.h"
#include "esp_eth_mac_ch390.h"
/** @note ----------------------- RX Pack Structure ---------------------------
* | 4 Bytes Frame Head | Data Area(pass to lwip) |
* | Head | Status | Length(Low) | Length(High) | ........ |
* | |
* | |
* | | Should be the value of RSR( @ref CH390_RSR). We use @ref RSR_ERR_MASK to determine
* | | whether the pack has error.
* | |-------------------------------------------------------------------------------------
* |
* | Depends on RCSEN bit( @ref RCSCSR_RCSEN) of RCSCSR( @ref CH390_RCSCSR)
* | - RCSEN = 0, the Head should always be 0x01
* | - RCSEN = 1, bit 7:2 of the Head is the same as that of RCSCSR;
* | This will affect the determination of the validity of the packet. Therefore,
* | we provide discriminant masks for both cases.
* | - RCSEN = 0 ---> @ref CH390_PKT_ERR
* | - RCSEN = 1 ---> @ref CH390_PKT_ERR_WITH_RCSEN
* |----------------------------------------------------------------------------------------------
*/
static const char *TAG = "ch390.mac";
#define CH390_SPI_LOCK_TIMEOUT_MS (50)
#define CH390_MAC_TX_WAIT_TIMEOUT_US (1000)
#define CH390_PHY_OPERATION_TIMEOUT_US (1000)
typedef struct {
uint8_t flag;
uint8_t status;
uint8_t length_low;
uint8_t length_high;
} ch390_rx_header_t;
typedef struct {
spi_device_handle_t hdl;
SemaphoreHandle_t lock;
} eth_spi_info_t;
typedef struct {
void *ctx;
void *(*init)(const void *spi_config);
esp_err_t (*deinit)(void *spi_ctx);
esp_err_t (*read)(void *spi_ctx, uint32_t cmd, uint32_t addr, void *data, uint32_t data_len);
esp_err_t (*write)(void *spi_ctx, uint32_t cmd, uint32_t addr, const void *data, uint32_t data_len);
} eth_spi_custom_driver_t;
typedef struct {
esp_eth_mac_t parent;
esp_eth_mediator_t *eth;
eth_spi_custom_driver_t spi;
TaskHandle_t rx_task_hdl;
uint32_t sw_reset_timeout_ms;
int int_gpio_num;
esp_timer_handle_t poll_timer;
uint32_t poll_period_ms;
uint8_t addr[ETH_ADDR_LEN];
bool flow_ctrl_enabled;
uint8_t *rx_buffer;
uint32_t rx_len;
} emac_ch390_t;
static inline bool CH390_SPI_LOCK(eth_spi_info_t *spi)
{
return xSemaphoreTake(spi->lock, pdMS_TO_TICKS(CH390_SPI_LOCK_TIMEOUT_MS)) == pdTRUE;
}
static inline bool CH390_SPI_UNLOCK(eth_spi_info_t *spi)
{
return xSemaphoreGive(spi->lock) == pdTRUE;
}
static void *CH390_SPI_INIT(const void *spi_config)
{
void *ret = NULL;
eth_ch390_config_t *ch390_config = (eth_ch390_config_t *)spi_config;
eth_spi_info_t *spi = calloc(1, sizeof(eth_spi_info_t));
ESP_GOTO_ON_FALSE(spi, NULL, err, TAG, "no memory for SPI context data");
/* SPI device init */
spi_device_interface_config_t spi_devcfg;
spi_devcfg = *(ch390_config->spi_devcfg);
if (ch390_config->spi_devcfg->command_bits == 0 && ch390_config->spi_devcfg->address_bits == 0) {
/* configure default SPI frame format */
spi_devcfg.command_bits = 1;
spi_devcfg.address_bits = 7;
} else {
ESP_GOTO_ON_FALSE(ch390_config->spi_devcfg->command_bits == 1 && ch390_config->spi_devcfg->address_bits == 7,
NULL, err, TAG, "incorrect SPI frame format (command_bits/address_bits)");
}
ESP_GOTO_ON_FALSE(spi_bus_add_device(ch390_config->spi_host_id, &spi_devcfg, &spi->hdl) == ESP_OK,
NULL, err, TAG, "adding device to SPI host #%d failed", ch390_config->spi_host_id + 1);
/* create mutex */
spi->lock = xSemaphoreCreateMutex();
ESP_GOTO_ON_FALSE(spi->lock, NULL, err, TAG, "create lock failed");
ret = spi;
return ret;
err:
if (spi) {
if (spi->lock) {
vSemaphoreDelete(spi->lock);
}
free(spi);
}
return ret;
}
static esp_err_t CH390_SPI_DEINIT(void *spi_ctx)
{
esp_err_t ret = ESP_OK;
eth_spi_info_t *spi = (eth_spi_info_t *)spi_ctx;
spi_bus_remove_device(spi->hdl);
vSemaphoreDelete(spi->lock);
free(spi);
return ret;
}
static inline esp_err_t CH390_SPI_WRITE(void *spi_ctx, uint32_t cmd, uint32_t addr, const void *value, uint32_t len)
{
esp_err_t ret = ESP_OK;
eth_spi_info_t *spi = (eth_spi_info_t *)spi_ctx;
spi_transaction_t trans = {
.cmd = cmd,
.addr = addr,
.length = 8 * len,
.tx_buffer = value
};
if (CH390_SPI_LOCK(spi)) {
if (spi_device_polling_transmit(spi->hdl, &trans) != ESP_OK) {
ESP_LOGE(TAG, "%s(%d): spi transmit failed", __FUNCTION__, __LINE__);
ret = ESP_FAIL;
}
CH390_SPI_UNLOCK(spi);
} else {
ret = ESP_ERR_TIMEOUT;
}
return ret;
}
static inline esp_err_t CH390_SPI_READ(void *spi_ctx, uint32_t cmd, uint32_t addr, void *value, uint32_t len)
{
esp_err_t ret = ESP_OK;
eth_spi_info_t *spi = (eth_spi_info_t *)spi_ctx;
spi_transaction_t trans = {
.cmd = cmd,
.addr = addr,
.length = 8 * len,
.rx_buffer = value
};
if (CH390_SPI_LOCK(spi)) {
if (spi_device_polling_transmit(spi->hdl, &trans) != ESP_OK) {
ESP_LOGE(TAG, "%s(%d): spi transmit failed", __FUNCTION__, __LINE__);
ret = ESP_FAIL;
}
CH390_SPI_UNLOCK(spi);
} else {
ret = ESP_ERR_TIMEOUT;
}
return ret;
}
/**
* @brief write value to ch390 internal register
*/
static esp_err_t ch390_io_register_write(emac_ch390_t *emac, uint8_t reg_addr, uint8_t value)
{
return emac->spi.write(emac->spi.ctx, CH390_SPI_WR, reg_addr, &value, 1);
}
/**
* @brief read value from ch390 internal register
*/
static esp_err_t ch390_io_register_read(emac_ch390_t *emac, uint8_t reg_addr, uint8_t *value)
{
return emac->spi.read(emac->spi.ctx, CH390_SPI_RD, reg_addr, value, 1);
}
/**
* @brief write buffer to ch390 internal memory
*/
static esp_err_t ch390_io_memory_write(emac_ch390_t *emac, uint8_t *buffer, uint32_t len)
{
return emac->spi.write(emac->spi.ctx, CH390_SPI_WR, CH390_MWCMD, buffer, len);
}
/**
* @brief read buffer from ch390 internal memory
*/
static esp_err_t ch390_io_memory_read(emac_ch390_t *emac, uint8_t *buffer, uint32_t len)
{
return emac->spi.read(emac->spi.ctx, CH390_SPI_RD, CH390_MRCMD, buffer, len);
}
IRAM_ATTR static void ch390_isr_handler(void *arg)
{
emac_ch390_t *emac = (emac_ch390_t *)arg;
BaseType_t high_task_wakeup = pdFALSE;
/* notify ch390 task */
vTaskNotifyGiveFromISR(emac->rx_task_hdl, &high_task_wakeup);
if (high_task_wakeup != pdFALSE) {
portYIELD_FROM_ISR();
}
}
static void ch390_poll_timer(void *arg)
{
emac_ch390_t *emac = (emac_ch390_t *)arg;
xTaskNotifyGive(emac->rx_task_hdl);
}
/**
* @brief read mac address from internal registers
*/
static esp_err_t ch390_get_mac_addr(emac_ch390_t *emac)
{
esp_err_t ret = ESP_OK;
for (int i = 0; i < ETH_ADDR_LEN; i++) {
ESP_GOTO_ON_ERROR(ch390_io_register_read(emac, CH390_PAR + i, &emac->addr[i]), err, TAG, "read PAR failed");
}
return ESP_OK;
err:
return ret;
}
/**
* @brief set new mac address to internal registers
*/
static esp_err_t ch390_set_mac_addr(emac_ch390_t *emac)
{
esp_err_t ret = ESP_OK;
for (int i = 0; i < 6; i++) {
ESP_GOTO_ON_ERROR(ch390_io_register_write(emac, CH390_PAR + i, emac->addr[i]), err, TAG, "write PAR failed");
}
return ESP_OK;
err:
return ret;
}
/**
* @brief clear multicast hash table
*/
static esp_err_t ch390_clear_multicast_table(emac_ch390_t *emac)
{
esp_err_t ret = ESP_OK;
/* rx broadcast packet control by bit7 of MAC register 1DH */
ESP_GOTO_ON_ERROR(ch390_io_register_write(emac, CH390_BCASTCR, 0x00), err, TAG, "write BCASTCR failed");
for (int i = 0; i < 7; i++) {
ESP_GOTO_ON_ERROR(ch390_io_register_write(emac, CH390_MAR + i, 0x00), err, TAG, "write MAR failed");
}
/* enable receive broadcast paclets */
ESP_GOTO_ON_ERROR(ch390_io_register_write(emac, CH390_MAR + 7, 0x80), err, TAG, "write MAR failed");
return ESP_OK;
err:
return ret;
}
/**
* @brief software reset ch390 internal register
*/
static esp_err_t ch390_reset(emac_ch390_t *emac)
{
esp_err_t ret = ESP_OK;
/* software reset */
uint8_t ncr = NCR_RST;
ESP_GOTO_ON_ERROR(ch390_io_register_write(emac, CH390_NCR, ncr), err, TAG, "write NCR failed");
uint32_t to = 0;
for (to = 0; to < emac->sw_reset_timeout_ms / 10; to++) {
ESP_GOTO_ON_ERROR(ch390_io_register_read(emac, CH390_NCR, &ncr), err, TAG, "read NCR failed");
if (!(ncr & NCR_RST)) {
break;
}
vTaskDelay(pdMS_TO_TICKS(10));
}
ESP_GOTO_ON_FALSE(to < emac->sw_reset_timeout_ms / 10, ESP_ERR_TIMEOUT, err, TAG, "reset timeout");
/* For CH390H/D, phy should be power on after software reset !*/
ESP_GOTO_ON_ERROR(ch390_io_register_write(emac, CH390_GPR, 0x00), err, TAG, "write GPR failed");
/* mac and phy register won't be accessible within at least 1ms */
vTaskDelay(pdMS_TO_TICKS(10));
return ESP_OK;
err:
return ret;
}
/**
* @brief verify ch390 chip ID
*/
static esp_err_t ch390_verify_id(emac_ch390_t *emac)
{
esp_err_t ret = ESP_OK;
uint8_t id[2];
ESP_GOTO_ON_ERROR(ch390_io_register_read(emac, CH390_VIDL, &id[0]), err, TAG, "read VIDL failed");
ESP_GOTO_ON_ERROR(ch390_io_register_read(emac, CH390_VIDH, &id[1]), err, TAG, "read VIDH failed");
ESP_GOTO_ON_FALSE(0x1C == id[1] && 0x00 == id[0], ESP_ERR_INVALID_VERSION, err, TAG, "wrong Vendor ID");
ESP_GOTO_ON_ERROR(ch390_io_register_read(emac, CH390_PIDL, &id[0]), err, TAG, "read PIDL failed");
ESP_GOTO_ON_ERROR(ch390_io_register_read(emac, CH390_PIDH, &id[1]), err, TAG, "read PIDH failed");
ESP_GOTO_ON_FALSE(0x91 == id[1] && 0x51 == id[0], ESP_ERR_INVALID_VERSION, err, TAG, "wrong Product ID");
return ESP_OK;
err:
return ret;
}
/**
* @brief default setup for ch390 internal registers
*/
static esp_err_t ch390_setup_default(emac_ch390_t *emac)
{
esp_err_t ret = ESP_OK;
/* disable wakeup */
ESP_GOTO_ON_ERROR(ch390_io_register_write(emac, CH390_NCR, 0x00), err, TAG, "write NCR failed");
ESP_GOTO_ON_ERROR(ch390_io_register_write(emac, CH390_WCR, 0x00), err, TAG, "write WCR failed");
/* stop transmitting, enable appending pad, crc for packets */
ESP_GOTO_ON_ERROR(ch390_io_register_write(emac, CH390_TCR, 0x00), err, TAG, "write TCR failed");
/* stop receiving, no promiscuous mode, no runt packet(size < 64bytes), receive all multicast packets */
/* discard long packet(size > 1522bytes) and crc error packet, enable watchdog */
ESP_GOTO_ON_ERROR(ch390_io_register_write(emac, CH390_RCR, RCR_DIS_CRC | RCR_ALL), err, TAG, "write RCR failed");
/* retry late collision packet, at most two transmit command can be issued before transmit complete */
ESP_GOTO_ON_ERROR(ch390_io_register_write(emac, CH390_TCR2, TCR2_RLCP), err, TAG, "write TCR2 failed");
/* generate checksum for UDP, TCP and IPv4 packets */
ESP_GOTO_ON_ERROR(ch390_io_register_write(emac, CH390_TCSCR, TCSCR_IPCSE | TCSCR_TCPCSE | TCSCR_UDPCSE), err, TAG, "write TCSCR failed");
/* disable check sum for receive packets */
ESP_GOTO_ON_ERROR(ch390_io_register_write(emac, CH390_RCSCSR, 0x00), err, TAG, "write RCSCSR failed");
/* interrupt pin config: push-pull output, active high */
ESP_GOTO_ON_ERROR(ch390_io_register_write(emac, CH390_INTCR, 0x00), err, TAG, "write INTCR failed");
ESP_GOTO_ON_ERROR(ch390_io_register_write(emac, CH390_INTCKCR, 0x00), err, TAG, "write INTCKCR failed");
/* set length limitation for rx packets to 1536(64*24)*/
ESP_GOTO_ON_ERROR(ch390_io_register_write(emac, CH390_RLENCR, RLENCR_RXLEN_EN | RLENCR_RXLEN_DEFAULT), err, TAG, "write RLENCR failed");
/* clear network status: wakeup event, tx complete */
ESP_GOTO_ON_ERROR(ch390_io_register_write(emac, CH390_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END), err, TAG, "write NSR failed");
return ESP_OK;
err:
return ret;
}
static esp_err_t ch390_enable_flow_ctrl(emac_ch390_t *emac, bool enable)
{
esp_err_t ret = ESP_OK;
if (enable) {
/* send jam pattern (duration time = 1.15ms) when rx free space < 3k bytes */
ESP_GOTO_ON_ERROR(ch390_io_register_write(emac, CH390_BPTR, 0x3F), err, TAG, "write BPTR failed");
/* flow control: high water threshold = 3k bytes, low water threshold = 8k bytes */
ESP_GOTO_ON_ERROR(ch390_io_register_write(emac, CH390_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8)), err, TAG, "write FCTR failed");
/* enable flow control */
ESP_GOTO_ON_ERROR(ch390_io_register_write(emac, CH390_FCR, FCR_FLOW_ENABLE), err, TAG, "write FCR failed");
} else {
/* disable flow control */
ESP_GOTO_ON_ERROR(ch390_io_register_write(emac, CH390_FCR, 0), err, TAG, "write FCR failed");
}
return ESP_OK;
err:
return ret;
}
static esp_err_t ch390_drop_frame(emac_ch390_t *emac, uint16_t length)
{
esp_err_t ret = ESP_OK;
uint8_t mrrh, mrrl;
ESP_GOTO_ON_ERROR(ch390_io_register_read(emac, CH390_MRRH, &mrrh), err, TAG, "read MDRAH failed");
ESP_GOTO_ON_ERROR(ch390_io_register_read(emac, CH390_MRRL, &mrrl), err, TAG, "read MDRAL failed");
uint16_t addr = mrrh << 8 | mrrl;
/* include 4B for header */
addr += length;
addr = addr < 0x4000 ? addr : addr - 0x3400;
ESP_GOTO_ON_ERROR(ch390_io_register_write(emac, CH390_MRRH, addr >> 8), err, TAG, "write MDRAH failed");
ESP_GOTO_ON_ERROR(ch390_io_register_write(emac, CH390_MRRL, addr & 0xFF), err, TAG, "write MDRAL failed");
err:
return ret;
}
/**
* @brief start ch390: enable interrupt and start receive
*/
static esp_err_t emac_ch390_start(esp_eth_mac_t *mac)
{
esp_err_t ret = ESP_OK;
emac_ch390_t *emac = __containerof(mac, emac_ch390_t, parent);
/* reset rx memory pointer */
ESP_GOTO_ON_ERROR(ch390_io_register_write(emac, CH390_MPTRCR, MPTRCR_RST_RX), err, TAG, "write MPTRCR failed");
/* clear interrupt status */
ESP_GOTO_ON_ERROR(ch390_io_register_write(emac, CH390_ISR, ISR_CLR_STATUS), err, TAG, "write ISR failed");
/* enable only Rx related interrupts as others are processed synchronously */
ESP_GOTO_ON_ERROR(ch390_io_register_write(emac, CH390_IMR, IMR_PAR | IMR_PRI), err, TAG, "write IMR failed");
/* enable rx */
uint8_t rcr = 0;
ESP_GOTO_ON_ERROR(ch390_io_register_read(emac, CH390_RCR, &rcr), err, TAG, "read RCR failed");
rcr |= RCR_RXEN;
ESP_GOTO_ON_ERROR(ch390_io_register_write(emac, CH390_RCR, rcr), err, TAG, "write RCR failed");
return ESP_OK;
err:
return ret;
}
/**
* @brief stop ch390: disable interrupt and stop receive
*/
static esp_err_t emac_ch390_stop(esp_eth_mac_t *mac)
{
esp_err_t ret = ESP_OK;
emac_ch390_t *emac = __containerof(mac, emac_ch390_t, parent);
/* disable interrupt */
ESP_GOTO_ON_ERROR(ch390_io_register_write(emac, CH390_IMR, 0x00), err, TAG, "write IMR failed");
/* disable rx */
uint8_t rcr = 0;
ESP_GOTO_ON_ERROR(ch390_io_register_read(emac, CH390_RCR, &rcr), err, TAG, "read RCR failed");
rcr &= ~RCR_RXEN;
ESP_GOTO_ON_ERROR(ch390_io_register_write(emac, CH390_RCR, rcr), err, TAG, "write RCR failed");
return ESP_OK;
err:
return ret;
}
static esp_err_t emac_ch390_set_mediator(esp_eth_mac_t *mac, esp_eth_mediator_t *eth)
{
esp_err_t ret = ESP_OK;
ESP_GOTO_ON_FALSE(eth, ESP_ERR_INVALID_ARG, err, TAG, "can't set mac's mediator to null");
emac_ch390_t *emac = __containerof(mac, emac_ch390_t, parent);
emac->eth = eth;
return ESP_OK;
err:
return ret;
}
static esp_err_t emac_ch390_write_phy_reg(esp_eth_mac_t *mac, uint32_t phy_addr, uint32_t phy_reg, uint32_t reg_value)
{
esp_err_t ret = ESP_OK;
emac_ch390_t *emac = __containerof(mac, emac_ch390_t, parent);
/* check if phy access is in progress */
uint8_t epcr = 0;
ESP_GOTO_ON_ERROR(ch390_io_register_read(emac, CH390_EPCR, &epcr), err, TAG, "read EPCR failed");
ESP_GOTO_ON_FALSE(!(epcr & EPCR_ERRE), ESP_ERR_INVALID_STATE, err, TAG, "phy is busy");
ESP_GOTO_ON_ERROR(ch390_io_register_write(emac, CH390_EPAR, (uint8_t)(CH390_PHY | phy_reg)), err, TAG, "write EPAR failed");
ESP_GOTO_ON_ERROR(ch390_io_register_write(emac, CH390_EPDRL, (uint8_t)(reg_value & 0xFF)), err, TAG, "write EPDRL failed");
ESP_GOTO_ON_ERROR(ch390_io_register_write(emac, CH390_EPDRH, (uint8_t)((reg_value >> 8) & 0xFF)), err, TAG, "write EPDRH failed");
/* select PHY and select write operation */
ESP_GOTO_ON_ERROR(ch390_io_register_write(emac, CH390_EPCR, EPCR_EPOS | EPCR_ERPRW), err, TAG, "write EPCR failed");
/* polling the busy flag */
uint32_t to = 0;
do {
esp_rom_delay_us(100);
ESP_GOTO_ON_ERROR(ch390_io_register_read(emac, CH390_EPCR, &epcr), err, TAG, "read EPCR failed");
to += 100;
} while ((epcr & EPCR_ERRE) && to < CH390_PHY_OPERATION_TIMEOUT_US);
ESP_GOTO_ON_FALSE(!(epcr & EPCR_ERRE), ESP_ERR_TIMEOUT, err, TAG, "phy is busy");
return ESP_OK;
err:
return ret;
}
static esp_err_t emac_ch390_read_phy_reg(esp_eth_mac_t *mac, uint32_t phy_addr, uint32_t phy_reg, uint32_t *reg_value)
{
esp_err_t ret = ESP_OK;
ESP_GOTO_ON_FALSE(reg_value, ESP_ERR_INVALID_ARG, err, TAG, "can't set reg_value to null");
emac_ch390_t *emac = __containerof(mac, emac_ch390_t, parent);
/* check if phy access is in progress */
uint8_t epcr = 0;
ESP_GOTO_ON_ERROR(ch390_io_register_read(emac, CH390_EPCR, &epcr), err, TAG, "read EPCR failed");
ESP_GOTO_ON_FALSE(!(epcr & 0x01), ESP_ERR_INVALID_STATE, err, TAG, "phy is busy");
ESP_GOTO_ON_ERROR(ch390_io_register_write(emac, CH390_EPAR, (uint8_t)(CH390_PHY | phy_reg)), err, TAG, "write EPAR failed");
/* Select PHY and select read operation */
ESP_GOTO_ON_ERROR(ch390_io_register_write(emac, CH390_EPCR, 0x0C), err, TAG, "write EPCR failed");
/* polling the busy flag */
uint32_t to = 0;
do {
esp_rom_delay_us(100);
ESP_GOTO_ON_ERROR(ch390_io_register_read(emac, CH390_EPCR, &epcr), err, TAG, "read EPCR failed");
to += 100;
} while ((epcr & EPCR_ERRE) && to < CH390_PHY_OPERATION_TIMEOUT_US);
ESP_GOTO_ON_FALSE(!(epcr & EPCR_ERRE), ESP_ERR_TIMEOUT, err, TAG, "phy is busy");
uint8_t value_h = 0;
uint8_t value_l = 0;
ESP_GOTO_ON_ERROR(ch390_io_register_read(emac, CH390_EPDRH, &value_h), err, TAG, "read EPDRH failed");
ESP_GOTO_ON_ERROR(ch390_io_register_read(emac, CH390_EPDRL, &value_l), err, TAG, "read EPDRL failed");
*reg_value = (value_h << 8) | value_l;
return ESP_OK;
err:
return ret;
}
static esp_err_t emac_ch390_set_addr(esp_eth_mac_t *mac, uint8_t *addr)
{
esp_err_t ret = ESP_OK;
ESP_GOTO_ON_FALSE(addr, ESP_ERR_INVALID_ARG, err, TAG, "can't set mac addr to null");
emac_ch390_t *emac = __containerof(mac, emac_ch390_t, parent);
memcpy(emac->addr, addr, 6);
ESP_GOTO_ON_ERROR(ch390_set_mac_addr(emac), err, TAG, "set mac address failed");
return ESP_OK;
err:
return ret;
}
static esp_err_t emac_ch390_get_addr(esp_eth_mac_t *mac, uint8_t *addr)
{
esp_err_t ret = ESP_OK;
ESP_GOTO_ON_FALSE(addr, ESP_ERR_INVALID_ARG, err, TAG, "can't set mac addr to null");
emac_ch390_t *emac = __containerof(mac, emac_ch390_t, parent);
memcpy(addr, emac->addr, 6);
return ESP_OK;
err:
return ret;
}
static esp_err_t emac_ch390_set_link(esp_eth_mac_t *mac, eth_link_t link)
{
esp_err_t ret = ESP_OK;
emac_ch390_t *emac = __containerof(mac, emac_ch390_t, parent);
switch (link) {
case ETH_LINK_UP:
ESP_GOTO_ON_ERROR(mac->start(mac), err, TAG, "ch390 start failed");
if (emac->poll_timer) {
ESP_GOTO_ON_ERROR(esp_timer_start_periodic(emac->poll_timer, emac->poll_period_ms * 1000),
err, TAG, "start poll timer failed");
}
break;
case ETH_LINK_DOWN:
ESP_GOTO_ON_ERROR(mac->stop(mac), err, TAG, "ch390 stop failed");
if (emac->poll_timer) {
ESP_GOTO_ON_ERROR(esp_timer_stop(emac->poll_timer),
err, TAG, "stop poll timer failed");
}
break;
default:
ESP_GOTO_ON_FALSE(false, ESP_ERR_INVALID_ARG, err, TAG, "unknown link status");
break;
}
return ESP_OK;
err:
return ret;
}
static esp_err_t emac_ch390_set_speed(esp_eth_mac_t *mac, eth_speed_t speed)
{
esp_err_t ret = ESP_OK;
switch (speed) {
case ETH_SPEED_10M:
ESP_LOGD(TAG, "working in 10Mbps");
break;
case ETH_SPEED_100M:
ESP_LOGD(TAG, "working in 100Mbps");
break;
default:
ESP_GOTO_ON_FALSE(false, ESP_ERR_INVALID_ARG, err, TAG, "unknown speed");
break;
}
return ESP_OK;
err:
return ret;
}
static esp_err_t emac_ch390_set_duplex(esp_eth_mac_t *mac, eth_duplex_t duplex)
{
esp_err_t ret = ESP_OK;
switch (duplex) {
case ETH_DUPLEX_HALF:
ESP_LOGD(TAG, "working in half duplex");
break;
case ETH_DUPLEX_FULL:
ESP_LOGD(TAG, "working in full duplex");
break;
default:
ESP_GOTO_ON_FALSE(false, ESP_ERR_INVALID_ARG, err, TAG, "unknown duplex");
break;
}
return ESP_OK;
err:
return ret;
}
static esp_err_t emac_ch390_set_promiscuous(esp_eth_mac_t *mac, bool enable)
{
esp_err_t ret = ESP_OK;
emac_ch390_t *emac = __containerof(mac, emac_ch390_t, parent);
uint8_t rcr = 0;
ESP_GOTO_ON_ERROR(ch390_io_register_read(emac, CH390_RCR, &rcr), err, TAG, "read RCR failed");
if (enable) {
rcr |= RCR_PRMSC;
} else {
rcr &= ~RCR_PRMSC;
}
ESP_GOTO_ON_ERROR(ch390_io_register_write(emac, CH390_RCR, rcr), err, TAG, "write RCR failed");
return ESP_OK;
err:
return ret;
}
static esp_err_t emac_ch390_enable_flow_ctrl(esp_eth_mac_t *mac, bool enable)
{
emac_ch390_t *emac = __containerof(mac, emac_ch390_t, parent);
emac->flow_ctrl_enabled = enable;
return ESP_OK;
}
static esp_err_t emac_ch390_set_peer_pause_ability(esp_eth_mac_t *mac, uint32_t ability)
{
emac_ch390_t *emac = __containerof(mac, emac_ch390_t, parent);
// we want to enable flow control, and peer does support pause function
// then configure the MAC layer to enable flow control feature
if (emac->flow_ctrl_enabled && ability) {
ch390_enable_flow_ctrl(emac, true);
}
else {
ch390_enable_flow_ctrl(emac, false);
ESP_LOGD(TAG, "Flow control not enabled for the link");
}
return ESP_OK;
}
static esp_err_t emac_ch390_transmit(esp_eth_mac_t *mac, uint8_t *buf, uint32_t length)
{
esp_err_t ret = ESP_OK;
emac_ch390_t *emac = __containerof(mac, emac_ch390_t, parent);
uint8_t tcr = 0;
ESP_GOTO_ON_FALSE(length <= ETH_MAX_PACKET_SIZE, ESP_ERR_INVALID_ARG, err,
TAG, "frame size is too big (actual %lu, maximum %u)",
length, ETH_MAX_PACKET_SIZE);
/* copy data to tx memory */
ESP_GOTO_ON_ERROR(ch390_io_memory_write(emac, buf, length), err, TAG,
"write memory failed");
/* Check if last transmit complete */
int64_t wait_time = esp_timer_get_time();
do {
ESP_GOTO_ON_ERROR(ch390_io_register_read(emac, CH390_TCR, &tcr), err, TAG,
"read TCR failed");
} while ((tcr & TCR_TXREQ) && ((esp_timer_get_time() - wait_time) < CH390_MAC_TX_WAIT_TIMEOUT_US));
if (tcr & TCR_TXREQ) {
ESP_LOGE(TAG, "last transmit still in progress, cannot send.");
return ESP_ERR_INVALID_STATE;
}
/* set tx length */
ESP_GOTO_ON_ERROR(ch390_io_register_write(emac, CH390_TXPLL, length & 0xFF), err, TAG, "write TXPLL failed");
ESP_GOTO_ON_ERROR(ch390_io_register_write(emac, CH390_TXPLH, (length >> 8) & 0xFF), err, TAG, "write TXPLH failed");
/* issue tx polling command */
ESP_GOTO_ON_ERROR(ch390_io_register_read(emac, CH390_TCR, &tcr), err, TAG, "read TCR failed");
ESP_GOTO_ON_ERROR(ch390_io_register_write(emac, CH390_TCR, tcr | TCR_TXREQ), err, TAG, "write TCR failed");
return ESP_OK;
err:
return ret;
}
static esp_err_t emac_ch390_receive(esp_eth_mac_t *mac, uint8_t *buf, uint32_t *length)
{
esp_err_t ret = ESP_OK;
emac_ch390_t *emac = __containerof(mac, emac_ch390_t, parent);
uint8_t ready;
/* dummy read, get the most updated data */
ESP_GOTO_ON_ERROR(ch390_io_register_read(emac, CH390_MRCMDX, &ready), err, TAG, "read MRCMDX failed");
ESP_GOTO_ON_ERROR(ch390_io_register_read(emac, CH390_MRCMDX, &ready), err, TAG, "read MRCMDX failed");
// if ready != 1 or 0 reset device
if (ready & CH390_PKT_ERR) {
emac_ch390_stop(mac);
esp_rom_delay_us(1000);
emac_ch390_start(mac);
ESP_LOGE(TAG, "PACK ERR");
return ESP_ERR_INVALID_RESPONSE;
} else {
__attribute__((aligned(4))) ch390_rx_header_t rx_header; // SPI driver needs the rx buffer 4 byte align
if (ready & CH390_PKT_RDY) {
ESP_GOTO_ON_ERROR(ch390_io_memory_read(emac, (uint8_t *) & (rx_header), sizeof(rx_header)),
err, TAG, "peek rx header failed");
*length = (rx_header.length_high << 8) + rx_header.length_low;
if (rx_header.status & RSR_ERR_MASK) {
ch390_drop_frame(emac, *length);
*length = 0;
return ESP_ERR_INVALID_RESPONSE;
} else if (*length > ETH_MAX_PACKET_SIZE) {
/* reset rx memory pointer */
ESP_GOTO_ON_ERROR(ch390_io_register_write(emac, CH390_MPTRCR, MPTRCR_RST_RX), err, TAG, "reset rx pointer failed");
return ESP_ERR_INVALID_RESPONSE;
} else {
ESP_GOTO_ON_ERROR(ch390_io_memory_read(emac, buf, *length), err, TAG, "read rx data failed");
*length -= ETH_CRC_LEN;
}
} else {
*length = 0;
}
return ESP_OK;
}
err:
*length = 0;
return ret;
}
static esp_err_t emac_ch390_init(esp_eth_mac_t *mac)
{
esp_err_t ret = ESP_OK;
emac_ch390_t *emac = __containerof(mac, emac_ch390_t, parent);
esp_eth_mediator_t *eth = emac->eth;
if (emac->int_gpio_num >= 0) {
esp_rom_gpio_pad_select_gpio(emac->int_gpio_num);
gpio_set_direction(emac->int_gpio_num, GPIO_MODE_INPUT);
gpio_set_pull_mode(emac->int_gpio_num, GPIO_PULLDOWN_ONLY);
gpio_set_intr_type(emac->int_gpio_num, GPIO_INTR_POSEDGE);
gpio_intr_enable(emac->int_gpio_num);
gpio_isr_handler_add(emac->int_gpio_num, ch390_isr_handler, emac);
}
ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_LLINIT, NULL), err, TAG, "lowlevel init failed");
/* reset ch390 */
ESP_GOTO_ON_ERROR(ch390_reset(emac), err, TAG, "reset ch390 failed");
/* verify chip id */
ESP_GOTO_ON_ERROR(ch390_verify_id(emac), err, TAG, "verify chip ID failed");
/* default setup of internal registers */
ESP_GOTO_ON_ERROR(ch390_setup_default(emac), err, TAG, "ch390 default setup failed");
/* clear multicast hash table */
ESP_GOTO_ON_ERROR(ch390_clear_multicast_table(emac), err, TAG, "clear multicast table failed");
/* get emac address from eeprom */
ESP_GOTO_ON_ERROR(ch390_get_mac_addr(emac), err, TAG, "fetch ethernet mac address failed");
return ESP_OK;
err:
if (emac->int_gpio_num >= 0) {
gpio_isr_handler_remove(emac->int_gpio_num);
gpio_reset_pin(emac->int_gpio_num);
}
eth->on_state_changed(eth, ETH_STATE_DEINIT, NULL);
return ret;
}
static esp_err_t emac_ch390_deinit(esp_eth_mac_t *mac)
{
emac_ch390_t *emac = __containerof(mac, emac_ch390_t, parent);
esp_eth_mediator_t *eth = emac->eth;
mac->stop(mac);
if (emac->int_gpio_num >= 0) {
gpio_isr_handler_remove(emac->int_gpio_num);
gpio_reset_pin(emac->int_gpio_num);
}
if (emac->poll_timer && esp_timer_is_active(emac->poll_timer)) {
esp_timer_stop(emac->poll_timer);
}
eth->on_state_changed(eth, ETH_STATE_DEINIT, NULL);
return ESP_OK;
}
static void emac_ch390_task(void *arg)
{
emac_ch390_t *emac = (emac_ch390_t *)arg;
uint8_t status = 0;
uint8_t *buffer;
while (1) {
// check if the task receives any notification
if (emac->int_gpio_num >= 0) { // if in interrupt mode
if (ulTaskNotifyTake(pdTRUE, pdMS_TO_TICKS(1000)) == 0 && // if no notification ...
gpio_get_level(emac->int_gpio_num) == 0) { // ...and no interrupt asserted
continue; // -> just continue to check again
}
} else {
ulTaskNotifyTake(pdTRUE, portMAX_DELAY);
}
/* clear interrupt status */
ch390_io_register_read(emac, CH390_ISR, &status);
ch390_io_register_write(emac, CH390_ISR, status);
/* packet received */
if (status & ISR_PR) {
do {
if (emac->parent.receive(&emac->parent, emac->rx_buffer, &emac->rx_len) == ESP_OK) {
if (emac->rx_len == 0) {
break;
} else {
ESP_LOGD(TAG, "receive len=%lu", emac->rx_len);
/* allocate memory and check whether allocation failed */
buffer = malloc(emac->rx_len);
if (buffer == NULL) {
ESP_LOGE(TAG, "no memory for receive buffer");
continue;
}
/* pass the buffer to stack (e.g. TCP/IP layer) */
memcpy(buffer, emac->rx_buffer, emac->rx_len);
emac->eth->stack_input(emac->eth, buffer, emac->rx_len);
}
} else {
ESP_LOGE(TAG, "frame read from module failed");
break;
}
} while (1);
}
}
vTaskDelete(NULL);
}
static esp_err_t emac_ch390_del(esp_eth_mac_t *mac)
{
emac_ch390_t *emac = __containerof(mac, emac_ch390_t, parent);
if (emac->poll_timer) {
esp_timer_delete(emac->poll_timer);
}
vTaskDelete(emac->rx_task_hdl);
emac->spi.deinit(emac->spi.ctx);
heap_caps_free(emac->rx_buffer);
free(emac);
return ESP_OK;
}
esp_eth_mac_t *esp_eth_mac_new_ch390(const eth_ch390_config_t *ch390_config, const eth_mac_config_t *mac_config)
{
esp_eth_mac_t *ret = NULL;
emac_ch390_t *emac = NULL;
ESP_GOTO_ON_FALSE(ch390_config, NULL, err, TAG, "can't set ch390 specific config to null");
ESP_GOTO_ON_FALSE(mac_config, NULL, err, TAG, "can't set mac config to null");
emac = calloc(1, sizeof(emac_ch390_t));
ESP_GOTO_ON_FALSE(emac, NULL, err, TAG, "calloc emac failed");
/* ch390 receive is driven by interrupt or timer signal */
ESP_GOTO_ON_FALSE((ch390_config->int_gpio_num >= 0) != (ch390_config->poll_period_ms > 0), NULL, err, TAG, "invalid configuration argument combination");
/* bind methods and attributes */
emac->sw_reset_timeout_ms = mac_config->sw_reset_timeout_ms;
emac->int_gpio_num = ch390_config->int_gpio_num;
emac->poll_period_ms = ch390_config->poll_period_ms;
emac->parent.set_mediator = emac_ch390_set_mediator;
emac->parent.init = emac_ch390_init;
emac->parent.deinit = emac_ch390_deinit;
emac->parent.start = emac_ch390_start;
emac->parent.stop = emac_ch390_stop;
emac->parent.del = emac_ch390_del;
emac->parent.write_phy_reg = emac_ch390_write_phy_reg;
emac->parent.read_phy_reg = emac_ch390_read_phy_reg;
emac->parent.set_addr = emac_ch390_set_addr;
emac->parent.get_addr = emac_ch390_get_addr;
emac->parent.set_speed = emac_ch390_set_speed;
emac->parent.set_duplex = emac_ch390_set_duplex;
emac->parent.set_link = emac_ch390_set_link;
emac->parent.set_promiscuous = emac_ch390_set_promiscuous;
emac->parent.set_peer_pause_ability = emac_ch390_set_peer_pause_ability;
emac->parent.enable_flow_ctrl = emac_ch390_enable_flow_ctrl;
emac->parent.transmit = emac_ch390_transmit;
emac->parent.receive = emac_ch390_receive;
if (ch390_config->custom_spi_driver.init != NULL && ch390_config->custom_spi_driver.deinit != NULL
&& ch390_config->custom_spi_driver.read != NULL && ch390_config->custom_spi_driver.write != NULL) {
ESP_LOGD(TAG, "Using user's custom SPI Driver");
emac->spi.init = ch390_config->custom_spi_driver.init;
emac->spi.deinit = ch390_config->custom_spi_driver.deinit;
emac->spi.read = ch390_config->custom_spi_driver.read;
emac->spi.write = ch390_config->custom_spi_driver.write;
/* Custom SPI driver device init */
ESP_GOTO_ON_FALSE((emac->spi.ctx = emac->spi.init(ch390_config->custom_spi_driver.config)) != NULL, NULL, err, TAG, "SPI initialization failed");
} else {
ESP_LOGD(TAG, "Using default SPI Driver");
emac->spi.init = CH390_SPI_INIT;
emac->spi.deinit = CH390_SPI_DEINIT;
emac->spi.read = CH390_SPI_READ;
emac->spi.write = CH390_SPI_WRITE;
/* SPI device init */
ESP_GOTO_ON_FALSE((emac->spi.ctx = emac->spi.init(ch390_config)) != NULL, NULL, err, TAG, "SPI initialization failed");
}
/* create ch390 task */
BaseType_t core_num = tskNO_AFFINITY;
if (mac_config->flags & ETH_MAC_FLAG_PIN_TO_CORE) {
core_num = esp_cpu_get_core_id();
}
BaseType_t xReturned = xTaskCreatePinnedToCore(emac_ch390_task, "ch390_tsk", mac_config->rx_task_stack_size, emac,
mac_config->rx_task_prio, &emac->rx_task_hdl, core_num);
ESP_GOTO_ON_FALSE(xReturned == pdPASS, NULL, err, TAG, "create ch390 task failed");
emac->rx_buffer = heap_caps_malloc(ETH_MAX_PACKET_SIZE, MALLOC_CAP_DMA);
ESP_GOTO_ON_FALSE(emac->rx_buffer, NULL, err, TAG, "RX buffer allocation failed");
if (emac->int_gpio_num < 0) {
const esp_timer_create_args_t poll_timer_args = {
.callback = ch390_poll_timer,
.name = "emac_spi_poll_timer",
.arg = emac,
.skip_unhandled_events = true
};
ESP_GOTO_ON_FALSE(esp_timer_create(&poll_timer_args, &emac->poll_timer) == ESP_OK, NULL, err, TAG, "create poll timer failed");
}
return &(emac->parent);
err:
if (emac) {
if (emac->rx_task_hdl) {
vTaskDelete(emac->rx_task_hdl);
}
if (emac->spi.ctx) {
emac->spi.deinit(emac->spi.ctx);
}
heap_caps_free(emac->rx_buffer);
free(emac);
}
return ret;
}

157
components/ETH_CH390H/esp_eth_phy_ch390.c Normal file
View File

@@ -0,0 +1,157 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*
* SPDX-FileContributor: 2024 Sergey Kharenko
* SPDX-FileContributor: 2024 Espressif Systems (Shanghai) CO LTD
*/
#include <string.h>
#include <stdlib.h>
#include <sys/cdefs.h>
#include "esp_log.h"
#include "esp_check.h"
#include "esp_eth_phy_802_3.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "esp_eth_phy_ch390.h"
#define CH390_INFO_OUI 0x1CDC64
#define CH390_INFO_MODEL 0x01
typedef struct {
phy_802_3_t phy_802_3;
} phy_ch390_t;
static const char *TAG = "ch390.phy";
static esp_err_t ch390_update_link_duplex_speed(phy_ch390_t *ch390)
{
esp_err_t ret = ESP_OK;
esp_eth_mediator_t *eth = ch390->phy_802_3.eth;
uint32_t addr = ch390->phy_802_3.addr;
eth_speed_t speed = ETH_SPEED_10M;
eth_duplex_t duplex = ETH_DUPLEX_HALF;
bmcr_reg_t bmcr;
bmsr_reg_t bmsr;
uint32_t peer_pause_ability = false;
anlpar_reg_t anlpar;
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_BMSR_REG_ADDR, &(bmsr.val)), err, TAG, "read BMSR failed");
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_BMSR_REG_ADDR, &(bmsr.val)), err, TAG, "read BMSR failed");
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_ANLPAR_REG_ADDR, &(anlpar.val)), err, TAG, "read ANLPAR failed");
eth_link_t link = bmsr.link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
/* check if link status changed */
if (ch390->phy_802_3.link_status != link) {
/* when link up, read negotiation result */
if (link == ETH_LINK_UP) {
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
if (bmcr.speed_select) {
speed = ETH_SPEED_100M;
} else {
speed = ETH_SPEED_10M;
}
if (bmcr.duplex_mode) {
duplex = ETH_DUPLEX_FULL;
} else {
duplex = ETH_DUPLEX_HALF;
}
ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_SPEED, (void *)speed), err, TAG, "change speed failed");
ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_DUPLEX, (void *)duplex), err, TAG, "change duplex failed");
/* if we're in duplex mode, and peer has the flow control ability */
if (duplex == ETH_DUPLEX_FULL && anlpar.symmetric_pause) {
peer_pause_ability = 1;
} else {
peer_pause_ability = 0;
}
ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_PAUSE, (void *)peer_pause_ability), err, TAG, "change pause ability failed");
}
ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_LINK, (void *)link), err, TAG, "change link failed");
ch390->phy_802_3.link_status = link;
}
return ESP_OK;
err:
return ret;
}
static esp_err_t ch390_get_link(esp_eth_phy_t *phy)
{
esp_err_t ret = ESP_OK;
phy_ch390_t *ch390 = __containerof(esp_eth_phy_into_phy_802_3(phy), phy_ch390_t, phy_802_3);
/* Update information about link, speed, duplex */
ESP_GOTO_ON_ERROR(ch390_update_link_duplex_speed(ch390), err, TAG, "update link duplex speed failed");
return ESP_OK;
err:
return ret;
}
static esp_err_t ch390_autonego_ctrl(esp_eth_phy_t *phy, eth_phy_autoneg_cmd_t cmd, bool *autonego_en_stat)
{
esp_err_t ret = ESP_OK;
phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
esp_eth_mediator_t *eth = phy_802_3->eth;
if (cmd == ESP_ETH_PHY_AUTONEGO_EN) {
bmcr_reg_t bmcr;
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, phy_802_3->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
ESP_GOTO_ON_FALSE(bmcr.en_loopback == 0, ESP_ERR_INVALID_STATE, err, TAG, "Auto-negotiation can't be enabled while in loopback operation");
}
return esp_eth_phy_802_3_autonego_ctrl(phy_802_3, cmd, autonego_en_stat);
err:
return ret;
}
static esp_err_t ch390_loopback(esp_eth_phy_t *phy, bool enable)
{
esp_err_t ret = ESP_OK;
phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
bool auto_nego_en = true;
ESP_GOTO_ON_ERROR(ch390_autonego_ctrl(phy, ESP_ETH_PHY_AUTONEGO_G_STAT, &auto_nego_en), err, TAG, "get status of autonegotiation failed");
ESP_GOTO_ON_FALSE(!(auto_nego_en && enable), ESP_ERR_INVALID_STATE, err, TAG,
"Unable to set loopback while auto-negotiation is enabled. Disable it to use loopback");
return esp_eth_phy_802_3_loopback(phy_802_3, enable);
err:
return ret;
}
static esp_err_t ch390_init(esp_eth_phy_t *phy)
{
esp_err_t ret = ESP_OK;
phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
/* Basic PHY init */
ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_basic_phy_init(phy_802_3), err, TAG, "failed to init PHY");
/* Check PHY ID */
uint32_t oui;
uint8_t model;
ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_read_oui(phy_802_3, &oui), err, TAG, "read OUI failed");
ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_read_manufac_info(phy_802_3, &model, NULL), err, TAG, "read manufacturer's info failed");
ESP_GOTO_ON_FALSE(oui == CH390_INFO_OUI && model == CH390_INFO_MODEL, ESP_FAIL, err, TAG, "wrong chip ID");
return ESP_OK;
err:
return ret;
}
esp_eth_phy_t *esp_eth_phy_new_ch390(const eth_phy_config_t *config)
{
esp_eth_phy_t *ret = NULL;
phy_ch390_t *ch390 = calloc(1, sizeof(phy_ch390_t));
ESP_GOTO_ON_FALSE(ch390, NULL, err, TAG, "calloc ch390 failed");
ESP_GOTO_ON_FALSE(esp_eth_phy_802_3_obj_config_init(&ch390->phy_802_3, config) == ESP_OK,
NULL, err, TAG, "configuration initialization of PHY 802.3 failed");
// override functions which need to be customized for sake of ch390
ch390->phy_802_3.parent.init = ch390_init;
ch390->phy_802_3.parent.get_link = ch390_get_link;
ch390->phy_802_3.parent.autonego_ctrl = ch390_autonego_ctrl;
ch390->phy_802_3.parent.loopback = ch390_loopback;
return &ch390->phy_802_3.parent;
err:
if (ch390 != NULL) {
free(ch390);
}
return ret;
}

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#include <stdio.h>
#include "esp_eth.h"
#include "esp_eth_driver.h"
#include "esp_eth_mac_ch390.h"
#include "esp_eth_phy_ch390.h"
#include "esp_netif.h"
#include "esp_event.h"
#include "driver/spi_master.h"
#include "esp_log.h"
#include "driver/gpio.h"
#define ETH_CS_GPIO (GPIO_NUM_10)
#define ETH_MOSI_GPIO (GPIO_NUM_12)
#define ETH_MISO_GPIO (GPIO_NUM_13)
#define ETH_SCLK_GPIO (GPIO_NUM_11)
#define ETH_INT_GPIO (GPIO_NUM_14)
#define SPI_HOST SPI2_HOST
#define SPI_CLOCK_MHZ 10
void eth_init(void);

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/*
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*
* SPDX-FileContributor: 2023-2024 NanjingQinhengMicroelectronics CO LTD
* SPDX-FileContributor: 2024 Sergey Kharenko
* SPDX-FileContributor: 2024-2025 Espressif Systems (Shanghai) CO LTD
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/********************************************************************
* Register definition
*/
#define CH390_NCR 0x00 // Network control reg
#define NCR_WAKEEN (1<<6) // Enable wakeup function
#define NCR_FDX (1<<3) // Duplex mode of the internal PHY
#define NCR_LBK_MAC (1<<1) // MAC loop-back
#define NCR_RST (1<<0) // Software reset
#define CH390_NSR 0x01 // Network status reg
#define NSR_SPEED (1<<7) // Speed of internal PHY
#define NSR_LINKST (1<<6) // Link status of internal PHY
#define NSR_WAKEST (1<<5) // Wakeup event status
#define NSR_TX2END (1<<3) // Tx packet B complete status
#define NSR_TX1END (1<<2) // Tx packet A complete status
#define NSR_RXOV (1<<1) // Rx fifo overflow
#define NSR_RXRDY (1<<0)
#define CH390_TCR 0x02 // Transmit control reg
#define TCR_TJDIS (1<<6) // Transmit jabber timer
#define TCR_PAD_DIS2 (1<<4) // PAD appends for packet B
#define TCR_CRC_DIS2 (1<<3) // CRC appends for packet B
#define TCR_PAD_DIS1 (1<<2) // PAD appends for packet A
#define TCR_CRC_DIS1 (1<<1) // CRC appends for packet A
#define TCR_TXREQ (1<<0) // Tx request
#define CH390_TSRA 0x03 // Transmit status reg A
#define CH390_TSRB 0x04 // Transmit status reg B
#define TSR_TJTO (1<<7) // Transmit jabber time out
#define TSR_LC (1<<6) // Loss of carrier
#define TSR_NC (1<<5) // No carrier
#define TSR_LCOL (1<<4) // Late collision
#define TSR_COL (1<<3) // Collision packet
#define TSR_EC (1<<2) // Excessive collision
#define CH390_RCR 0x05 // Receive control reg
#define RCR_DEFAULT 0x00 // Default settings
#define RCR_WTDIS (1<<6) // Disable 2048 bytes watch dog
#define RCR_DIS_CRC (1<<4) // Discard CRC error packet
#define RCR_ALL (1<<3) // Pass all multicast
#define RCR_RUNT (1<<2) // Pass runt packet
#define RCR_PRMSC (1<<1) // Promiscuous mode
#define RCR_RXEN (1<<0) // Enable RX
#define CH390_RSR 0x06 // Receive status reg
#define RSR_RF (1<<7) // Rnt frame
#define RSR_MF (1<<6) // Multicast frame
#define RSR_LCS (1<<5) // Late collision seen
#define RSR_RWTO (1<<4) // Receive watchdog time-out
#define RSR_PLE (1<<3) // Physical layer error
#define RSR_AE (1<<2) // Alignment error
#define RSR_CE (1<<1) // CRC error
#define RSR_FOE (1<<0) // FIFO overflow error
//Receive status error mask(default)
#define RSR_ERR_MASK (RSR_RF | RSR_LCS | RSR_RWTO | RSR_PLE | \
RSR_AE | RSR_CE | RSR_FOE)
#define CH390_ROCR 0x07 // Receive overflow count reg
#define CH390_BPTR 0x08 // Back pressure threshold reg
#define CH390_FCTR 0x09 // Flow control threshold reg
#define FCTR_HWOT(overflow_th) (( overflow_th & 0xf ) << 4)
#define FCTR_LWOT(overflow_th) ( overflow_th & 0xf )
#define CH390_FCR 0x0A // Transmit/Receive flow control reg
#define FCR_FLOW_ENABLE (0x39) // Enable Flow Control
#define CH390_EPCR 0x0B // EEPROM or PHY control reg
#define EPCR_REEP (1<<5) // Reload EEPROM
#define EPCR_WEP (1<<4) // Write EEPROM enable
#define EPCR_EPOS (1<<3) // EEPROM or PHY operation select
#define EPCR_ERPRR (1<<2) // EEPROM or PHY read command
#define EPCR_ERPRW (1<<1) // EEPROM or PHY write command
#define EPCR_ERRE (1<<0) // EEPROM or PHY access status
#define CH390_EPAR 0x0C // EEPROM or PHY address reg
#define CH390_EPDRL 0x0D // EEPROM or PHY low byte data reg
#define CH390_EPDRH 0x0E // EEPROM or PHY high byte data reg
#define CH390_WCR 0x0F // Wakeup control reg
#define WCR_LINKEN (1<<5) // Link status change wakeup
#define WCR_SAMPLEEN (1<<4) // Sample frame wakeup
#define WCR_MAGICEN (1<<3) // Magic packet wakeup
#define WCR_LINKST (1<<2) // Link status change event
#define WCR_SAMPLEST (1<<1) // Sample frame event
#define WCR_MAGICST (1<<0) // Magic packet event
#define CH390_PAR 0x10 // MAC address reg
#define CH390_MAR 0x16 // Multicast address reg
#define CH390_GPCR 0x1E // General purpose control reg
#define CH390_GPR 0x1F // General purpose reg
#define CH390_TRPAL 0x22 // Transmit read pointer low byte address reg
#define CH390_TRPAH 0x23 // Transmit read pointer high byte address reg
#define CH390_RWPAL 0x24 // Receive write pointer low byte address reg
#define CH390_RWPAH 0x25 // Receive write pointer high byte address reg
#define CH390_VIDL 0x28 // Vendor ID low byte reg
#define CH390_VIDH 0x29 // Vendor ID high byte reg
#define CH390_PIDL 0x2A // Product ID low byte reg
#define CH390_PIDH 0x2B // Product ID high byte reg
#define CH390_CHIPR 0x2C // Chip reversion reg
#define CH390_TCR2 0x2D // Transmit control reg II
#define TCR2_RLCP (1<<6) // Retry Late Collision Packet
#define CH390_ATCR 0x30 // Auto-Transmit control reg
#define ATCR_AUTO_TX (1<<7) // Auto-Transmit Control
#define CH390_TCSCR 0x31 // Transmit checksum and control reg
#define TCSCR_ALL 0x1F
#define TCSCR_IPv6TCPCSE (1<<4) // IPv6 TCP checksum generation
#define TCSCR_IPv6UDPCSE (1<<3) // IPv6 UDP checksum generation
#define TCSCR_UDPCSE (1<<2) // UDP checksum generation
#define TCSCR_TCPCSE (1<<1) // TCP checksum generation
#define TCSCR_IPCSE (1<<0) // IP checksum generation
#define CH390_RCSCSR 0x32 // Receive checksum and control reg
#define RCSCSR_UDPS (1<<7) // UDP checksum status
#define RCSCSR_TCPS (1<<6) // TCP checksum status
#define RCSCSR_IPS (1<<5) // IP checksum status
#define RCSCSR_UDPP (1<<4) // UDP packet of current received packet
#define RCSCSR_TCPP (1<<3) // TCP packet of current received packet
#define RCSCSR_IPP (1<<2) // IP packet of current received packet
#define RCSCSR_RCSEN (1<<1) // Receive checksum checking enable
#define RCSCSR_DCSE (1<<0) // Discard checksum error packet
#define CH390_MPAR 0x33 // MII PHY address reg
#define CH390_SBCR 0x38 // SPI bus control reg
#define CH390_INTCR 0x39 // INT pin control reg
#define INCR_TYPE_OD 0x02 // Open drain output
#define INCR_TYPE_PP 0x00 // Push pull output
#define INCR_POL_L 0x01 // Low level positive
#define INCR_POL_H 0x00 // High level positive
#define CH390_ALNCR 0x4A // SPI alignment error count reg
#define CH390_SCCR 0x50 // System clock control reg
#define CH390_RSCCR 0x51 // Recover system clock control reg
#define CH390_RLENCR 0x52 // Receive data pack length control reg
#define RLENCR_RXLEN_EN 0x80 // Enable RX data pack length filter
#define RLENCR_RXLEN_DEFAULT 0x18 // Default MAX length of RX data(div by 64)
#define CH390_BCASTCR 0x53 // Receive broadcast control reg
#define CH390_INTCKCR 0x54 // INT pin clock output control reg
#define CH390_MPTRCR 0x55 // Memory pointer control reg
#define MPTRCR_RST_TX (1<<1) // Reset TX Memory Pointer
#define MPTRCR_RST_RX (1<<0) // Reset RX Memory Pointer
#define CH390_MLEDCR 0x57 // More LED control reg
#define CH390_MRCMDX 0x70 // Memory read command without address increment reg
// Memory read command without data pre-fetch and address increment reg
#define CH390_MRCMDX1 0x71
#define CH390_MRCMD 0x72 // Memory data read command with address increment reg
#define CH390_MRRL 0x74 // Memory read low byte address reg
#define CH390_MRRH 0x75 // Memory read high byte address reg
#define CH390_MWCMDX 0x76 // Memory write command without address increment reg
#define CH390_MWCMD 0x78 // Memory write command
#define CH390_MWRL 0x7A // Memory write low byte address reg
#define CH390_MWRH 0x7B // Memory write high byte address reg
#define CH390_TXPLL 0x7C // Transmit pack low byte length reg
#define CH390_TXPLH 0x7D // Transmit pack high byte length reg
#define CH390_ISR 0x7E // Interrupt status reg
#define ISR_LNKCHG (1<<5) // Link status change
#define ISR_ROO (1<<3) // Receive overflow counter overflow
#define ISR_ROS (1<<2) // Receive overflow
#define ISR_PT (1<<1) // Packet transmitted
#define ISR_PR (1<<0) // Packet received
#define ISR_CLR_STATUS (ISR_LNKCHG | ISR_ROO | ISR_ROS | ISR_PT | ISR_PR)
#define CH390_IMR 0x7F // Interrupt mask reg
#define IMR_NONE 0x00 // Disable all interrupt
#define IMR_ALL 0xFF // Enable all interrupt
#define IMR_PAR (1<<7) // Pointer auto-return mode
#define IMR_LNKCHGI (1<<5) // Enable link status change interrupt
#define IMR_UDRUNI (1<<4) // Enable transmit under-run interrupt
#define IMR_ROOI (1<<3) // Enable receive overflow counter overflow interrupt
#define IMR_ROI (1<<2) // Enable receive overflow interrupt
#define IMR_PTI (1<<1) // Enable packet transmitted interrupt
#define IMR_PRI (1<<0) // Enable packet received interrupt
// SPI commands
#define OPC_REG_W 0x80 // Register Write
#define OPC_REG_R 0x00 // Register Read
#define OPC_MEM_DMY_R 0x70 // Memory Dummy Read
#define OPC_MEM_WRITE 0xF8 // Memory Write
#define OPC_MEM_READ 0x72 // Memory Read
#define CH390_SPI_RD 0
#define CH390_SPI_WR 1
// GPIO
#define CH390_GPIO1 0x02
#define CH390_GPIO2 0x04
#define CH390_GPIO3 0x08
// PHY registers
#define CH390_PHY 0x40
#define CH390_PHY_BMCR 0x00
#define CH390_PHY_BMSR 0x01
#define CH390_PHY_PHYID1 0x02
#define CH390_PHY_PHYID2 0x03
#define CH390_PHY_ANAR 0x04
#define CH390_PHY_ANLPAR 0x05
#define CH390_PHY_ANER 0x06
#define CH390_PHY_PAGE_SEL 0x1F
// Packet status
#define CH390_PKT_NONE 0x00 /* No packet received */
#define CH390_PKT_RDY 0x01 /* Packet ready to receive */
#define CH390_PKT_ERR 0xFE /* Un-stable states mask */
#define CH390_PKT_ERR_WITH_RCSEN 0xE2 /* Un-stable states mask when RCSEN = 1 */
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*
* SPDX-FileContributor: 2024 Sergey Kharenko
* SPDX-FileContributor: 2024 Espressif Systems (Shanghai) CO LTD
*/
#pragma once
#include "esp_eth_com.h"
#include "esp_eth_mac.h"
#include "esp_idf_version.h"
#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 3, 0)
#include "esp_eth_mac_spi.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief CH390 specific configuration
*
*/
typedef struct {
int int_gpio_num; /*!< Interrupt GPIO number */
uint32_t poll_period_ms; /*!< Period in ms to poll rx status when interrupt mode is not used */
spi_host_device_t spi_host_id; /*!< SPI peripheral (this field is invalid when custom SPI driver is defined) */
spi_device_interface_config_t *spi_devcfg; /*!< SPI device configuration (this field is invalid when custom SPI driver is defined) */
eth_spi_custom_driver_config_t custom_spi_driver; /*!< Custom SPI driver definitions */
} eth_ch390_config_t;
/**
* @brief Default CH390 specific configuration
*
*/
#define ETH_CH390_DEFAULT_CONFIG(spi_host, spi_devcfg_p) \
{ \
.int_gpio_num = 4, \
.spi_host_id = spi_host, \
.spi_devcfg = spi_devcfg_p, \
.custom_spi_driver = ETH_DEFAULT_SPI, \
}
/**
* @brief Create CH390 Ethernet MAC instance
*
* @param ch390_config: CH390 specific configuration
* @param mac_config: Ethernet MAC configuration
*
* @return
* - instance: create MAC instance successfully
* - NULL: create MAC instance failed because some error occurred
*/
esp_eth_mac_t *esp_eth_mac_new_ch390(const eth_ch390_config_t *ch390_config, const eth_mac_config_t *mac_config);
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*
* SPDX-FileContributor: 2024 Sergey Kharenko
* SPDX-FileContributor: 2024 Espressif Systems (Shanghai) CO LTD
*/
#pragma once
#include "esp_eth_com.h"
#include "esp_eth_phy.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Create a PHY instance of CH390
*
* @param[in] config: configuration of PHY
*
* @return
* - instance: create PHY instance successfully
* - NULL: create PHY instance failed because some error occurred
*/
esp_eth_phy_t *esp_eth_phy_new_ch390(const eth_phy_config_t *config);
#ifdef __cplusplus
}
#endif